The main goal of computer-aided design simulations is the device electrical characteristics. The device dimensions which have significant impact on the electrical characteristics include, for example, gate oxide thickness, gate width, and length, shape of the poly gate at the bottom, and spacer width. Semiconductor fabrication techniques have advanced so much as to create fairly simple geometrical shapes for these features. As a result, simple geometrical etch rules have been sufficient for these critical dimensions of the device. As device dimensions continue to shrink, semiconductor fabrication processes or techniques require more complex techniques to meet the design goals. In one particular area, the topography on the wafer created by various fabrication processes has become increasingly important.
As the device size shrinks, especially into the deep-submicron regime, the electric properties of wires become more prominent, and chips are more susceptive to breakdown during fabrication due to, for example, antenna effect or to wear out over time due to, for example, electro-migration. Some prior methods proposed prioritizing the nets and forcing shorter wire lengths among the high-priority, timing critical nets. However, making certain wires shorter usually comes at the expense of making other wires longer. Some other prior methods use larger gates with bigger transistors and higher drive strengths to charge the capacitance of wire more quickly and therefore making the path faster to maintain timing correctness without overly shortening some wires while lengthening others. However, one problem exists for these methods. In electronic designs, the actual wire lengths are not known until some gates are physically in place. Nonetheless, because larger gates also have larger capacitance and thus increases both timing delay and power dissipated, the above solution does not satisfactorily solve the problems caused by increasingly shrinking feature sizes.
Another problem with using larger gates is that larger gates with larger drive strength tend to worsen the problem of electro-migration. Deposited aluminum and copper interconnect have a polycrystalline structure from most fabrication processes; that is, these aluminum and copper interconnects are made of small grain lattices. Metal atoms can be transported between the grain boundaries. Electro-migration occurs during the momentum exchange between the mobile carriers and the atomic lattice as the current flow through the interconnect. As a result of the momentum exchange, metal tends to deposit in the direction of the electron flow, and voids thus form at the grain boundaries and reduce the conductivity. Such voids may over time cause the interconnect to stop conducting electricity altogether and thus cause the interconnect to fail.
Moreover, the continual effort to scale down to the deep submicron region requires multilevel interconnection architecture to minimize the time delay due to parasitic resistance and capacitance. As the devices shrinks smaller, the delay caused by the increased R-C time constant becomes more significant over the delay caused by the actual wire length. In order to reduce the R-C time constant, interconnect materials with low resistivity and interlayer films with low capacitance are required. However, the use of low-k dielectric material aggravates the electro-migration problem due to the poor thermal conductivity of these low-k dielectric materials.
One way of resolving the aforementioned problems introduced by the continual reduction in feature sizes is to impose certain density rules for metal filling. Such rules typically comprise certain maximum and minimum densities within certain windows on the chip. Some other rules impose different density limits among different window areas. FIG. 1 illustrates an example of such design rules involving percentages of metal densities. At step 102, the designer receives a set of foundry-imposed design rules which specify the minimum and maximum of metal densities in a window of certain size. It shall be noted that the design rule requiring metal density be within 20-60% in 102 merely represents an example for illustrative purposes.
At 104, designer builds the design based upon the foundry-imposed design rules. The designer then sends the design to fabrication and hopes that the design would work as designed, 106. However, such rules typically assume that the thickness of the wire is constant according to certain formulae and therefore manipulate only the width of the wires to achieve the design goals. Although this assumption arises out of a practical consideration, such an assumption appears to be outdated, especially in light of the current development in incorporating the topological variations of each film into the electronic designs and the continuously shrinkage in sizes of device features. Moreover, wire width cannot be arbitrarily changed due to the polycrystalline structure of the interconnect materials. As a result, additional methods have been developed to slot certain wires such that the metal density within certain region falls within the prescribed maximum and minimum limits.
Nonetheless, the above rule-based methods pose new problems. For instance, a good interconnect may be wrongfully determined to be improper for failing to meet the density rules or for producing unacceptable R-C delay even though the interconnect actually satisfies the design goals or design intent by having certain thickness that is different from the assumed value. A contrary example is that a bad interconnect may also be wrongfully determined to be proper for meeting the metal density rules and/or the delay requirement. As a result, there exists a need for a more accurate and effective method for supplanting the above rule-based design criteria and replacing these methods with a new and improved method which takes into account the topographical variation of the films and a new set of rules incorporating thicknesses of the films or other characteristics of the features of a feature in an electronic design.
Moreover, chemical mechanical polishing (CMP) is an important planarization technique for integrated circuit manufacturing. Conventionally, in order for CMP to work properly, the layout must be made uniform with respect to certain density parameters. As a result, foundries typically impose metal density requirements as mandatory design rules that must be satisfied prior to tapeout. Such design rules may be one that requires, for example, the metal density be within 20-60% within an arbitrarily placed square area of certain size. Such design rules exhibit, however, several disadvantages in the sense that they may outlaw some perfectly good designs in some cases and legalize some bad designs in others. Furthermore, even among legal designs which are within such limits, designers may nonetheless prefer different metal thicknesses in different parts of their designs.
For example, a designer might prefer thin metal where minimum capacitance (C) is needed, and thick metal where minimum resistance (R) is required. A density limit, as typically specified by the foundries now, does not tell how the thickness depends on density and does not express any relationship between density and thickness, not even the sign of any such relationship. Moreover, with the introduction of dual-damascene processes, the combination of electroplating (or electrochemical deposition, ECD) and CMP processes which are applied to create multi-material interconnect create even more complex pattern dependencies that include features such as line width and line perimeter. For example, an array of 0.12 micron copper lines at 50% density may not polish to the same topographical profile as an array of one micron copper lines at 50% density.
The elimination of etch stops also created more complex pattern and process interaction that results in variation in the bottom of the etched interconnect features, particularly with regard to linewidth geometries. Thickness may be impacted by variation on the top of the surface as a result of CMP, such as the topology of the layer processed by CMP, or in the bottom of certain etched features.